1. Field of the Invention
Embodiments of the present invention generally relate to a method of manufacturing a semiconductor device. More particularly, the invention is directed to a method of thermally processing a substrate.
2. Description of the Related Art
The market for semiconductor devices continues to follow the path of Moore's Law. Current device geometry of 45 nanometers (nm) is projected to shrink to 20 nm and beyond to meet future performance requirements. For such scaling to be realized, engineering of doped source and drain junctions must focus on placement and movement of single atoms within a very small crystal lattice. For example, some future device designs contemplate channel regions comprising fewer than 100 atoms. With such exacting requirements, controlling placement of dopant atoms to within a few atomic radii is needed.
Placement of dopant atoms is controlled currently by processes of implanting dopants into source and drain regions of silicon substrates and then annealing the substrates. Dopants may be used to enhance electrical conductivity in a silicon matrix, to induce damage to a crystal structure, or to control diffusion between layers. Atoms such as boron (B), phosphorus (P), arsenic (As), cobalt (Co), indium (In), and antimony (Sb) may be used for enhanced conductivity. Silicon (Si), germanium (Ge), and argon (Ar) may be used to induce crystal damage. For diffusion control, carbon (C), fluorine (F), and nitrogen (N) are commonly used. During annealing, a substrate is typically heated to high temperatures so that various chemical and physical reactions can take place in multiple IC devices defined in the substrate. Annealing recreates a more crystalline structure from regions of the substrate that were previously made amorphous, and “activates” dopants by incorporating their atoms into the crystalline lattice of the substrate. Ordering the crystal lattice and activating dopants reduces resistivity of the doped regions. Thermal processes, such as annealing, involve directing a relatively large amount of thermal energy onto a substrate in a short amount of time, and thereafter rapidly cooling the substrate to terminate the thermal process. Examples of thermal processes that have been widely used for some time include Rapid Thermal Processing (RTP) and impulse (spike) annealing. Although widely used, such processes are not ideal because they ramp the temperature of the wafer too slowly and expose the wafer to elevated temperatures for too long. These problems become more severe with increasing wafer sizes, increasing switching speeds, and/or decreasing feature sizes.
In general, conventional thermal processes heat the substrates under controlled conditions according to a predetermined thermal recipe. These thermal recipes fundamentally consist of a target temperature for the semiconductor substrate, the rate of change of temperature, i.e., the temperature ramp-up and ramp-down rates, and the time that the thermal processing system remains at a particular temperature. For example, thermal recipes may require the substrate to be heated from room temperature to a peak temperature of 1200° C. or more, and may require processing times near each peak temperature ranging up to 60 seconds, or more.
The objective of all processes for annealing doped substrates is to generate enough movement of atoms within the substrate to cause dopant atoms to occupy crystal lattice positions, and to cause silicon atoms to reorder themselves into a crystalline pattern, without allowing dopant atoms to diffuse broadly through the substrate. Such broad diffusion reduces the electrical performance of the doped regions by reducing concentration of dopants and spreading them through a larger region of the substrate. To accomplish these objectives, the temperature ramp rates, both up and down, are preferably high. In other words, it is desirable to be able to adjust the temperature of the substrate from a low to a high temperature, or visa versa, in as short a time as possible. Current anneal processes are generally able to preserve concentration abruptness of about 3-4 nm/decade (10% change) of concentration. As junction depth shrinks to less than 100 Angstroms, however, future abruptness less than 2 nm/decade is of interest.
The need for high temperature ramp rates led to the development of Rapid Thermal Processing (RTP), where typical temperature ramp-up rates range from 200 to 400° C./s, as compared to 5-15° C./minute for conventional furnaces. Typical ramp-down rates are in the range of 80-150° C./s. Although the IC devices reside only in the top few microns of the substrate, RTP heats the entire substrate. This limits how fast one can heat and cool the substrate. Moreover, once the entire substrate is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, today's state of the art RTP systems struggle to achieve a 400° C./s ramp-up rate and a 150° C./s ramp-down rate.
Impulse and spike annealing have been utilized to accelerate temperature ramping further. Energy is delivered to one portion of the substrate over a very short time in a single impulse. In order to deliver enough energy to result in substantial annealing, however, large energy densities are required. For example, impulse annealing may require energy density delivered to the substrate above about 2 J/cm2. Delivering enough energy to substantially anneal the substrate in a single short-duration pulse often results in significant damage to its surface. Moreover, delivering very short impulses of energy to the substrate can lead to problems of uniformity. Further, the energy needed to activate dopants may be very different from the energy needed to order the crystal lattice. Finally, shrinking device dimensions leads to over-diffusion of dopants beyond the junction region with even impulse and spike anneals.
Some have tried annealing a substrate using two or more pulses of energy, wherein a first pulse of energy may be designed to approximate the energy needed to activate dopants, and subsequent pulses individually adjusted in either intensity or duration to achieve a target thermal history of the substrate with the objective of ordering the crystal lattice. Such efforts have reported only limited success. It is thought that pulses delivering different amounts of energy, while promoting organization of the crystal lattice, may work to undo dopant activation accomplished in the first impulse. The differing modes of energy delivered by the impulses may excite different modes of movement within the crystal lattice that may generally remove crystal defects while dislodging some dopant atoms from their activated positions. Uniformity of treatment is also difficult to achieve.
To resolve some of the problems raised in conventional RTP-type processes various scanning laser anneal techniques have been used to anneal the surface(s) of the substrate. In general, these techniques deliver a constant energy flux to a small region on the surface of the substrate while the substrate is translated, or scanned, relative to the energy delivered to the small region. Even delivering constant energy flux to each region, uniform processing is difficult to achieve because the anneal regions have differing thermal histories. Regions treated first have thermal history comprising a sharp spike followed by long heat-soak, regions treated last have long heat-soak followed by sharp spike, and those in the middle have heat-soak/spike/heat-soak histories. Due to the stringent uniformity requirements and the complexity of minimizing the overlap of scanned regions across the substrate surface these types of processes are not effective for thermal processing of next-generation contact level devices formed on the surface of the substrate.
Moreover, as the size of the various elements in semiconductor devices decreases with the need to increase device speed, the normal conventional annealing techniques that allow rapid heating and cooling are not effective. In a future generation device with a channel region comprising 60 atoms, traditional notions of temperature and thermal gradients, generally based on statistical treatments of molecular translational energy in a material body, do not apply because of the gradation in the area in which the energy is to be transferred. Traditional RTP and laser anneal processes raise the substrate temperature to between about 1150-1350° C. for only about one second to remove damage in the substrate and achieve a desired dopant distribution. In one process step, these conventional methods seek to heat the substrate to a relatively high temperature and then rapidly cool it in a relatively short period of time. To ensure that a desired dopant distribution remains within the these small device regions one would need to devise a way to heat and cool the substrate rapidly between a peak anneal temperature, which is typically between about 1150-1200° C. for RTP processes, and a temperature that prevents continuing diffusion of the dopant atoms (e.g., <750° C.) in less than about 0.02 to about 1 second. Heating and cooling the substrate at these high rates is generally impossible with standard thermal treatment processes because a substrate will generally take about 0.5 seconds to cool down on its own. To induce more rapid cooling, it is necessary to apply a cooling medium, which in turn requires massive amounts of energy to heat the substrate to the target temperature. Even without the cooling medium, the energy required to maintain the temperature of a substrate at a high level using conventional techniques is formidable. Treating only portions of a substrate at one time reduces the energy budget, but generates stresses in the substrate that makes it break.
In view of the above, there is a need for a method of annealing a semiconductor substrate that has sufficient energy delivery control to allow the anneal of small devices, and an apparatus capable of performing that method. This will achieve the necessary control over the fabrication of smaller devices that will lead to increased performance.